RISC V CPU Design -Sr Engineer

Company Qualcomm India Private Limited

Job Area Engineering Group, Engineering Group > Hardware Engineering

General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices using the RISC-V Architecture. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle.

Roles And Responsibilities

• Performance exploration. Explore high performance strategies working with the CPU modeling team.
• Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.
• RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
• Functional verification support. Help the design verification team execute on the functional verification strategy.
• Performance verification support. Help verify that the RTL design meets the performance goals.
• Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability and testability.

Preferred Qualifications

• Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems
• Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools
• Knowledge of logic design principles along with timing and power implications
• Understanding of low power microarchitecture techniques
• Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
• Experience using a scripting language such as Perl or Python

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore.

Roles and Responsibilities

• Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.
• Work closely with design/verification teams within CPU to develop comprehensive test plan.
• Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.
• Verify power intent through use of methodologies like UPF.
• Work closely with system architects, software teams and Soc team to validate system use cases.
• Work closely with emulation team to enable verification on emulators and FPGA platforms.
• Debug and triage failures in simulation, emulation and/or Silicon.

BE/BTech degree in CS/EE with 3+ years’ experience.

• Experience in power management verification.
• Implementation of assembly and C language embedded firmware.
• Experience in C/C++, scripting languages, Verilog/system Verilog.
• Strong understanding of power management features in CPUs and CPU based Socs.
• Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

Preferred Requirements

• Good Understanding of CPU architectures and CPU micro-architectures.
• In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture
• Experience with advanced verification techniques such as formal and assertions is a plus
• Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

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