Senior Principle DV Engineer

NXP Semiconductors•Pune Division, Maharashtra, India

fulltime

Engineering and Information Technology

15+ years

About the role

Job Title: Senior Design Verification Architect / Senior Principal DV Engineer Location: [Pune, India ]

Role Overview We are seeking a highly experienced Design Verification (DV) Architect with 20+ years of expertise to lead verification strategy and execution for complex SoCs. The ideal candidate will have deep knowledge of ARM-based microcontrollers , low-power design verification , and experience with multiple interfaces and security IPs. This is a hands-on role requiring strong technical skills, leadership, and collaboration in a fast-paced environment.

Key Responsibilities

Define and own SoC-level and IP-level verification strategy, methodology, and coverage goals.
Hands-on work:
Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.
Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and nalyze code/functional coverage
Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
Familiar with both SoC-level and IP-level verification environments.
Guide the team in developing and improving flows for maximum reuse and efficiency.
Mentor team members while actively collaborating with design teams for issue resolution and sign-off.
Ensure compliance with functional safety/security requirements.

Required Qualifications

Experience: 15 to 20 years in SoC/IP verification with successful tape-outs of multiple SoCs.
Technical Skills:

Strong expertise in ARM-based microcontrollers and SoC-level verification.
Proficiency in SystemVerilog, UVM, and constrained-random verification.
Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa).
Experience with low-power verification (UPF).
Gate-level simulations and power-aware simulations.
Strong knowledge of assertions (SVA) and functional coverage.
Verification of multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI.
Knowledge of Flash memory and security IPs.
Familiarity with common Analog IPs in microcontroller design (ADC, DAC, PLLs).

Soft Skills:

Comfortable working in a fast-paced environment.
Strong team player with excellent communication skills.

Education: Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering or Computer Engineering.

More information about NXP in India...

Similar Opportunities

About NXP Semiconductors

Visit Website