The
High Voltage Power (HVP)
team at TI develops power solutions with hundreds of volts of withstand capability. We offer one of the world's largest portfolios, including:
High-performance AC/DC and isolated DC/DC controllers.
GaN-integrated
power-stages and converters.
Modules with a wide range of power topology options.
The Opportunity:
This is a
new investment area for TI in India
. You will be part of an exciting startup-like ecosystem, gaining the experience of building a team and technical expertise under the safety of the wider TI umbrella.
What Will You Be Doing? (Responsibilities)
Verification Planning:
Develop detailed coverage-driven Verification plans working closely with System and Design teams.
Behavioral Modeling:
Model analog blocks using
SV RNM and VerilogAMS
(wreal, electrical).
System Testing:
Identify and develop system-level tests in AMS to ensure bug-free silicon.
Testbench Development:
Independently develop
SV/UVM
based testbenches, tests, checkers, and assertions with randomization.
Innovation:
Drive new DV methodologies and collaborate with the EDA team to upgrade tools/flows.
Collaboration:
Interact with Test/Validation for post-silicon activities and customer debug/analysis.
Leadership:
Mentor junior peers and collaborate with Digital Design, Firmware, and Analog teams.
What Do We Expect From You? (Qualifications)
Fundamentals:
Strong knowledge of mixed-signal design, analog building blocks, and digital design processes.
UVM Mastery:
Experience developing mixed-signal testbenches in
SV/UVM
with the capability to debug and optimize simulation performance.
Debug Capability:
Strong ability to analyze simulation waveforms and pinpoint issues in schematics or models.
Ownership:
Ability to handle design deliverables and schedules independently.
Education:
Bachelor’s / Master’s in Electrical or Electronics Engineering.
Mindset:
Self-driven, strong communicator, and a thirst for continuous learning.
Preferred Skills & Experience
Experience:
2–5 years in Mixed-Signal Design Verification.
AMS Tech:
Experience with
SOC-AMS
testbench development and regression flows.
Cadence Toolset:
Expertise in
Virtuoso, ADE Assembler, Xcelium, VIVA, and Simvision
.
Language & Scripting:
Excellence in
System Verilog, UVM, and VerilogAMS
; proficiency in Python, Perl, Tcl, or Shell scripting.
ATS Match is available
1) Upload your resume. 2) Open any job and click Check ATS Match to see your fit score.