Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SILICON DESIGN ENGINEER The Role Are you passionate about pushing the boundaries of power efficiency and high-frequency computing? As a part of our AMD physical design central methodology team, you can help define timing, power, and clocking methodologies for our next-generation, high-performance cores, graphics and machine intelligence chips. This team collaborates across AMD, working on projects ranging from low power APUs to the world’s most powerful supercomputers.

The Person In this multi-functional role, you will have the opportunity to work across multiple divisions to drive physical design methodology optimizations across the entire physical design space (library/technology/flows/design). We’re looking for someone with excellent attention to detail, passion and curiosity to resolve complex issues while achieving amazing results!

Key Responsibilities Responsibilities may include a subset of the following topics:

• Drive PVT corners/ frequency targets while considering various product performance modes and guard bands
• Drive IP physical implementation recipes from synthesis to route to achieve the best performance/watt
• RTL (architecture) and PD co-development to identify bottlenecks
• Drive budgeting, measurement, analysis and tracking of power-consumption
• Establish global methodologies and best-known physical implementation recipes for optimal performance/watt across library/flow/Synthesis/P&R environment
• Drive best practices for global/local clock distribution methodologies including skew/power/jitter trade-off’s
• Create guidelines on clocking/timing/power sign-off methodologies

Preferred Experience

• Expertise in these topics would be a plus:
• Design experience in sub-micron processes
• Familiarity with CPU and or GPU architecture
• Hands on experience with power-analysis and measurement tools like Prime Power and or Power-Artist
• Experience with high performance clocking
• STA methodologies for timing closure, OCV and other advanced statistical margining techniques
• Proficiency in scripting languages such as Perl/Tcl/Python
• Proficiency in data analysis and interpretation

Academic Responsibilities

• MS/PhD degree in Electrical Engineering is preferred
• Mastery of logic, circuit design, and CAD tools for high-performance design is expected.

LOCATION: Austin, TX; Boston, MA; Santa Clara, CA; Ft. Collins, CO or Markham, CN

This role is not eligible for Visa sponsorship. Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.