RTL Synthesis and constraints Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER

The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Job Title: RTL Synthesis and constraints Lead Location: Hyderabad

Employment Type: Full-Time

About The Role Looking for strong RTL designer having 7-10 years of experience for timing constraint design and sign-off with Physical design team for an SOC subsystem . This role require strong digital design and SOC quality and constraint development for various for Processor and Interconnect based system design that also includes peripherals. The preference is for candidates who have delivered and worked for SOC design as Subsystem Timing constraint Lead and understands SOC constraints requirements. The selected person will own subsystem constraint development, debug and sign-off for SOCs in deep sub-micron technology.

Key Responsibilities

• Develop timing constraints for Subsystem for SOC
• Work with RTL leads and use or define best practices for constraint development
• Collaborate with Physical design and DFT constraints team members for timing sign-off
• Ensure timely delivery of projects while meeting quality standards.
• Provide strong technical solution to internal and external stakeholders.

Preferred Experience – 7-10 Years

• Proven experience in SOC timing lead role with focus on Timing closure of subsystem IP and delivery to SOC to PD teams
• Expertise and strong understanding of RTL quality checks and constraints debug for Subsystem IP
• Excellent communication skill
• Strong analytical and problem-solving abilities, including designing experiments for performance
• Self-motivated and proactive in driving initiatives.

Academic Credentials

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.