Principle/Staff STA Engineer

Job Summary We are seeking a highly skilled and experienced Principle/Staff STA Engineer to join our dynamic team in Noida. This role involves leading and executing Static Timing Analysis (STA) for complex SoC designs, ensuring timing closure, and contributing to the development of next-generation semiconductor products.

Job Responsibilities

• Lead and perform comprehensive Static Timing Analysis (STA) at the block, sub-system, and SoC levels for cutting-edge semiconductor designs.
• Develop, integrate, and maintain timing constraints (SDC) for various design hierarchies, ensuring accuracy and coverage.
• Identify, debug, and resolve complex timing violations, including setup, hold, and other advanced timing checks (e.g., OCV, AOCV, EMIR, X-talk).
• Collaborate closely with design, DFT, physical design, and verification teams to ensure timing closure and meet project deadlines.
• Develop and implement efficient STA methodologies, flows, and scripts to improve productivity and turnaround time.
• Perform timing sign-off activities and generate comprehensive timing reports for internal and external reviews.
• Mentor and provide technical guidance to junior engineers, fostering a culture of continuous learning and improvement.
• Stay updated with industry trends, best practices, and new technologies in STA and physical design.

Job Qualifications

• Bachelor's or Master's degree in Electronics Engineering, or a related field.
• For Staff Engineer: 6+ years of relevant experience in Static Timing Analysis (STA) on complex SoC designs.
• For Principle Engineer: 9+ years of relevant experience in Static Timing Analysis (STA) with a proven track record of leading and driving timing closure for multiple successful tape-outs.
• Expert-level proficiency with industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).
• Strong understanding of timing analysis concepts, including clock tree synthesis, critical path analysis, signal integrity, and process variations.
• Hands-on experience with SDC (Synopsys Design Constraints) generation, debugging, and optimization.
• Proficiency in scripting languages such as Tcl, Perl, and Python for flow automation and data analysis.
• Solid understanding of physical design concepts, including floorplanning, placement, routing, and their impact on timing.
• Experience with various technology nodes (e.g., 28nm, 16nm, 7nm, 5nm).
• Excellent problem-solving, analytical, and debugging skills.
• Strong communication and interpersonal skills, with the ability to collaborate effectively in a global team environment.
• Experience in a leadership or mentorship role (for Principle Engineer).

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