Lead Physical Design Engineer

NXP Semiconductors•Pune Division, Maharashtra, India

fulltime

Engineering and Information Technology

8+ years

About the role

Job Summary We are seeking a highly experienced Principal PD Engineer for iMCU & Connectivity to lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits. This role involves driving technical solutions, mentoring junior engineers, and ensuring the timely delivery of cutting-edge products within NXP's diverse portfolio.

Job Responsibilities As a Senior PD Engineer, your responsibilities will include but are not limited to:

Will be responsible for block level floor planning, power grid design, place and route, low power implementation, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna).
The role would involve in-depth knowledge and responsibilities spanning all aspects of physical implementation.
Drive the definition and implementation of physical design methodologies, flows, and best practices to optimize performance, power, and area.
Perform comprehensive static timing analysis (STA) and ensure all timing constraints are met across various corners and modes.
Conduct power integrity (IR drop) and signal integrity (Crosstalk) analysis and implement solutions to mitigate issues.
Oversee and perform design rule checking (DRC), layout versus schematic (LVS), and other physical verification steps to ensure tape-out readiness.
Collaborate closely with architecture, RTL design, DFT, and package teams to ensure seamless integration and successful product delivery.
Mentor and provide technical guidance to junior and senior physical design engineers, fostering a culture of continuous learning and excellence.
Evaluate and adopt new EDA tools and technologies to improve design efficiency and quality.

Job Qualifications

Bachelor's degree with 9+ years of professional experience or Master's degree with 8+ years of professional experience.
Working knowledge on advance tech nodes 16ff and below is highly desirable.
Extensive knowledge and experience in back-end implementation tasks such as (timing & power), synthesis, low power implementation, power analysis, equivalence checking and STA.
Experience at top-level will be added advantage.
Expert-level proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI).
Deep understanding of Static Timing Analysis (STA) concepts, sign-off criteria, and tools (e.g., Synopsys PrimeTime).
Strong knowledge of power analysis and optimization techniques (e.g., UPF/CPF, clock gating, power intent).
Proven experience with physical verification tools (e.g., Synopsys IC Validator, Cadence Pegasus/PVS, Mentor Calibre).
Solid understanding of semiconductor device physics, process technology effects, and DFM/DFY considerations.
Proficiency in scripting languages (e.g., Tcl, Python, Perl) for automation of design flows and analysis.
Excellent problem-solving, analytical, and debugging skills.
Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and mentor other engineers.
Ability to work independently and take ownership of critical design aspects.

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