WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
The Role
AMD is seeking a Senior Formal Verification Engineer to own formal verification for complex GFXIP blocks
and contribute to subsystem sign-off in partnership with FV tech leads. You will work closely with design and architecture
to translate specifications into robust properties, improve convergence, and raise verification quality for high-impact blocks.
The Person
- Self-directed engineer who can own a complex block’s formal plan, make sound technical decisions, and drive closure with limited supervision
- Clear communicator who conveys status, risks, and recommendations to cross-functional partners
- Analytical problem-solver skilled at tackling difficult convergence and debug challenges
- Collaborative team player who supports peers and shares reusable assets and best practices
Key Responsibilities
- Own formal verification plans and execution for one or more complex GFXIP blocks; support subsystem sign-off with guidance from FV tech leads
- Develop properties and constraints from architectural/design specs; partner with designers to clarify intent and improve verifiability
- Build and maintain high-quality formal testbenches and assertion suites; ensure property soundness, non-vacuity, and constraint hygiene
- Apply advanced formal techniques (abstraction, cutpoints, invariants, assume‑guarantee, cone-of-influence reduction) to improve convergence and throughput
- Drive closure on formal quality metrics for assigned blocks: proof convergence, property completeness, functional/code coverage; contribute to app-based checks (connectivity, CDC/RDC, X‑prop) and equivalence checking as needed
- Debug counterexamples efficiently; provide actionable feedback and collaborate on RTL/design fixes; prevent regressions through reviews and targeted automation
- Contribute to methodology and automation via reusable assertion libraries, scripts, checklists, and CI integrations; share learnings across the team
- Provide guidance to junior engineers through reviews, pairing, and knowledge sharing
- Document verification plans, assumptions, findings, and lessons learned; provide clear status updates and risk/mitigation plans to stakeholders
Preferred Experience
- Digital design/verification with a demonstrated experience on the formal verification
- Proven ownership of formal verification for complex blocks in GPU/CPU or high-performance IP; contribution to subsystem-level sign-off
- Proficiency with formal tools: Cadence JasperGold, Synopsys VC Formal; familiarity with SEC and formal apps (connectivity, CDC/RDC, X‑prop, deadlock/liveness)
- Strong SystemVerilog Assertions (SVA) skills; experience deriving properties from specs and building reusable assertion frameworks
- Hands-on convergence techniques and counterexample debug; experience with abstraction/invariants/assume‑guarantee
- Scripting skills (Python, TCL); experience with automation and CI to scale formal runs and metrics
- Solid understanding of processor/GPU microarchitecture, memory systems, interfaces, and power/clock/reset domains
Academic Credentials
- Bachelors or Masters degree in Computer Engineering/Electrical Engineering
LOCATION
- Cambridge, United Kingdom (Hybrid)
Benefits offered are described:
AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
