EDA Software Engineer – RTL Static Verification (Lint/CDC)

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER

The Role The focus of this role is to plan, develop, and regress AMD EDA tools in the area of RTL static checks and the framework. This tool is required to be run by all SoC in AMD to ensure RTL quality.

THE PERSON:

You have a passion for solving engineering problems and flair for digital design using System Verilog and static RTL checks. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Own development and qualification of the Static RTL quality checking tool using ensuring production‑ready quality and scalability.
• Integrate the tool into frontend and verification flows through close collaboration with RTL, verification, and methodology teams.
• Design and execute large‑scale tool‑qualification regressions on AMD SoC designs, validating correctness across use cases and configurations.
• Build and maintain regression automation, infrastructure, and reporting to improve efficiency and debuggability.
• Enable frontend, static, and power‑aware design flows, including SystemVerilog, UPF, SDC timing constraints, and tools such as Lint, CDC, RDC, LEC, VCLP/CLP, and Fishtail‑TCM.

PREFERRED EXPERIENCE:

• Knowledge in RTL Lint, CDC and other static tools and flows
• Knowledgable in System Verilog HDLs and Python, Perl, Tcl, and shell scripting.
• Proficient in debugging RTL issues and in using static tools.
• Exposure of static flows and working in Linux and Windows environments
• Good working knowledge of Verilog, System Verilog and VHDL
• Good understanding and hands-on experience in the static vendor tools for lint, CDC/RDC, TCM etc

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Electronics Engineering or Computer engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.