Design For Test (DFT) Engineer at Samsung Electronic… | creonjobs.com
temporary Posted January 30, 2026
Design For Test (DFT) Engineer $270k - $270k/year About Samsung Electronics Resume Tailoring
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Design For Test (DFT) Engineer – Contractor
📍
San Diego, CA | Onsite 5 Days
💰
Pay Range: up to $130/hr
Contract Duration 6 months
Who We’re Looking For
The ideal candidate is a
hands-on DFT Engineer
with strong end-to-end ownership of
test architecture, implementation, debug, and silicon bring-up
for complex SoCs—specifically in
RF and Bluetooth/Wireless LAN chipsets
. This individual works comfortably across
Front-End RTL, Physical Design, and Test teams
, and can independently drive DFT solutions from concept to production.
Core Technical Strengths
DFT Implementation & Methodology Deep experience with
Memory BIST using Siemens Tessent
Strong hands-on expertise in
scan compression
(SEQ / Ultra / TestKompress)
Advanced
ATPG
experience using
Tetramax
Proven skills in
ATPG diagnosis
,
ATE debug
, and
silicon bring-up
Experience with
DFT pattern translation (VTRAN)
Design & Verification Solid
RTL design experience
using
Verilog / SystemVerilog
Strong understanding of
gate-level simulation
and simulation debug
Working knowledge of
STA and timing concepts
, including:
CDC analysis
Clock gating checks
Timing constraints using
PrimeTime
Automation & Productivity Strong scripting skills in
Tcl, Perl, and/or Python
Ability to automate DFT flows, debug processes, and validation checks
Professional Attributes
5+ years of relevant industry experience
in DFTStrong
problem-solving and root-cause analysis
skills
Comfortable working
independently with minimal supervision
Excellent collaboration skills with
FE, PD, and silicon teams
Ability to work
onsite full-time (5 days/week)
in San Diego
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