Company Qualcomm India Private Limited
Job Area Engineering Group, Engineering Group > Hardware Engineering
General Summary Join our team building next-generation CPU verification solutions for cutting-edge RISC-V processors.
Location: Bangalore , Santa-Clara.
What You’ll Do Design and implement a configurable instruction generator for RISC-V ISA.
Enable automated test generation for functional and microarchitectural coverage.
Support custom ISA extensions and advanced features.
Integrate with simulation/emulation environments for high-performance verification.
What We’re Looking For Strong understanding of RISC-V architecture and ISA.
Proficiency in Python/C++ (bonus: experience with DSLs or generator frameworks).
Familiarity with verification flows, random instruction generation, and coverage-driven methodologies.
Passion for open-source and CPU design innovation.
Why Join Us?
Work on open standards and contribute to the RISC-V ecosystem.
Collaborate with world-class architects and verification engineers.
Opportunity to innovate and influence verification strategies for complex SoCs.
Minimum Qualifications
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
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