RTL Design Lead for High speed IO designs (HBM, DDR, GDDR memory PHYs)

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER The Role As part of Circuits and Technology group, the ideal candidate will get to work on design of complex high speed Analog Mixed Signal IPs (with significant Digital and Analog content) that are delivered to various AMD SoCs.

Key Responsiblities

• Design and develop RTL code for DDR blocks in Verilog HDL and make sure they are functionally correct and reusable for different configurations based on architectural requirements.
• Conduct design reviews of designs in technical presentations to peers and management
• Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure.
• Work with Design Verification team to ensure quality for architecture definition and design implementation.

Preferred Experience

• MS or BS in Electrical Engineering/Computer Engineering/ Computer Science with 10+ years working experience in ASIC design industry.
• Knowledge in computer architecture and interconnects.
• Experience in high speed IO controller design (e.g. DDR, USB, PCIe, SATA, Ethernet). DDR experience is plus.
• Experience in full ASIC design cycle: Understanding spec requirement, RTL, design verification, floor-planning, synthesis, timing closure, power intent, post-silicon validation
• Expert on Verilog RTL design and has experience of large digital ASIC project.
• Familiar with front-end EDA tools and flows.
• Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.)
• Excellent interpersonal, communication, and writing skills. Able to provide clear and logical presentations and documentation. Has an open mind and attitude. Transparent. Willing to admit and learn from mistakes.
• Works well with others in a team environment
• Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as committed milestones.

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.