Senior ASIC RTL Design Engineer

AMD•Santa Clara, CA

fulltime

Engineering, Information Technology, and Design

5+ years

About the role

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role As a member of the SBIO front‑end design and integration team, you will collaborate with architecture, IP design, physical design, and product engineering teams to develop and deliver high‑quality IP for SOC products. In this role, you will contribute to design, integration, documentation, and cross‑functional coordination to help achieve first‑pass silicon success.

The Person We welcome applicants with experience in digital design, processor architecture, and verification who enjoy solving complex technical challenges. Ideal candidates communicate clearly, work effectively in cross‑site or distributed teams, and are comfortable learning new skills as technologies evolve.

Key Responsiblities

Design RTL for high‑speed digital blocks, including clock, reset, and power‑related features.
Architect and implement power‑management features and low‑power RTL techniques.
Integrate IP blocks at the subsystem level and resolve inter‑IP design and integration issues.
Manage clock‑domain crossing and linting activities for IP and subsystem designs.
Collaborate with FEINT, DFT, Physical Design, and SOC teams to incorporate feedback across disciplines.
Contribute to architecture, microarchitecture, and design documentation.
Provide clear status updates and participate in team‑based problem‑solving activities.

Preferred Experience

Background in digital IP/ASIC design and Verilog‑based RTL development.
Familiarity with the full IP design cycle, including requirements, architecture, verification, and validation.
Understanding of RTL verification, design‑quality checks, synthesis, timing closure, and post‑silicon validation.
Experience with front‑end EDA tools, sign‑off flows, and low‑power design methodologies.
Working knowledge of scripting languages such as Python or Perl.
Ability to collaborate effectively on cross‑functional teams and manage multiple technical tasks.
Ability to create clear technical documentation in English.
Understanding of semiconductor engineering terminology and digital design concepts.
Knowledge of or experience with functional design verification.

Academic Credentials

Bachelors or Master's degree in computer engineering/Electrical Engineering or equivalent field of study.

This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

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